irL1404S irl1404l hexfet ? power mosfet seventh generation hexfet ? power mosfets from international rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the d 2 pak is a surface mount power package capable of accommodating die sizes up to hex-4. it provides the highest power capability and the lowest possible on- resistance in any existing surface mount package. the d 2 pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0w in a typical surface mount application. the through-hole version (irl1404l) is available for low- profile applications. s d g parameter max. units i d @ t c = 25 c continuous drain current, v gs @ 10v 160 i d @ t c = 100 c continuous drain current, v gs @ 10v 110 a i dm pulsed drain current 640 p d @t a = 25 c power dissipation 3.8 w p d @t c = 25 c power dissipation 200 w linear derating factor 1.3 w/ c v gs gate-to-source voltage 20 v e as single pulse avalanche energy 520 mj i ar avalanche current 95 a e ar repetitive avalanche energy 20 mj dv/dt peak diode recovery dv/dt 5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case) c absolute maximum ratings thermal resistance v dss = 40v r ds(on) = 0.004 ? i d = 160a advanced process technology ultra low on-resistance dynamic dv/dt rating 175 c operating temperature fast switching fully avalanche rated description 02/22/02 pd - 93854a www.irf.com 1 d 2 pak irL1404S to-262 irl1404l parameter typ. max. units r jc junction-to-case ??? 0.75 r cs case-to-sink, flat, greased surface 0.50 ??? c/w r ja junction-to-ambient (pcb mounted) ??? 40
irL1404S/irl1404l 2 www.irf.com parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 40 ??? ??? vv gs = 0v, i d = 250a ? v (br)dss / ? t j breakdown voltage temp. coefficient ??? 0.038 ??? v/ c reference to 25 c, d = 1ma r ds(on) static drain-to-source on-resistance ??? ??? 0.004 ? v gs = 10v, i d = 95a 0.0059 v gs = 4.3v, i d = 40a v gs(th) gate threshold voltage 1.0 ??? 3.0 v v ds = v gs , i d = 250a g fs forward transconductance 93 ??? ??? sv ds = 25v, i d = 95a ??? ??? 20 a v ds = 40v, v gs = 0v ??? ??? 250 v ds = 32v, v gs = 0v, t j = 150 c gate-to-source forward leakage ??? ??? 200 v gs = 20v gate-to-source reverse leakage ??? ??? -200 na v gs = -20v q g total gate charge ??? ??? 140 i d = 95a q gs gate-to-source charge ??? ??? 48 nc v ds = 32v q gd gate-to-drain ("miller") charge ??? ??? 60 v gs = 5.0v, see fig. 6 t d(on) turn-on delay time ??? 18 ??? v dd = 20v t r rise time ??? 270 ??? i d = 95a t d(off) turn-off delay time ??? 38 ??? r g = 2.5 ? v gs = 4.5v t f fall time ??? 130 ??? r d = 0.25 ? between lead, ??? ??? 6mm (0.25in.) from package and center of die contact c iss input capacitance ??? 6600 ??? v gs = 0v c oss output capacitance ??? 1700 ??? pf v ds = 25v c rss reverse transfer capacitance ??? 350 ??? ? = 1.0mhz, see fig. 5 c oss output capacitance ??? 6700 ??? v gs = 0v, v ds = 1.0v, ? = 1.0mhz c oss output capacitance ??? 1500 ??? v gs = 0v, v ds = 32v, ? = 1.0mhz c oss eff. effective output capacitance ??? 1500 ??? v gs = 0v, v ds = 0v to 32v nh electrical characteristics @ t j = 25c (unless otherwise specified) l d internal drain inductance l s internal source inductance ??? ??? s d g i gss ns 4.5 7.5 i dss drain-to-source leakage current s d g parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) ??? ??? showing the i sm pulsed source current integral reverse (body diode) ??? ??? p-n junction diode. v sd diode forward voltage ??? ??? 1.3 v t j = 25 c, i s = 95a, v gs = 0v t rr reverse recovery time ??? 63 94 ns t j = 25 c, i f = 95a q rr reverse recoverycharge ??? 170 250 nc di/dt = 100a/s t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) source-drain ratings and characteristics 160 640 a
irL1404S/irl1404l www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0.0 0.5 1.0 1.5 2.0 2.5 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d 10v 160a 10 100 1000 0.1 1 10 100 20 s pulse width t = 25 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.3v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.3v 10 100 1000 0.1 1 10 100 20 s pulse width t = 175 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.3v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.3v 100 1000 4.0 5.0 6.0 7.0 8.0 v = 15v 20 s pulse width ds v , gate-to-source volta g e (v) i , drain-to-source current (a) gs d t = 25 c j t = 175 c j
irL1404S/irl1404l 4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 0 2000 4000 6000 8000 10000 v , drain-to-source volta g e (v) c, capacitance (pf) ds v c c c = = = = 0v, c c c f = 1mhz + c + c c shorted gs iss g s g d , ds rss g d oss ds g d c iss c oss c rss 0 100 200 300 400 500 0 4 8 12 16 20 q , total gate char g e (nc) v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 95a v = 20v ds v = 32v ds 1 10 100 1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ,source-to-drain volta g e (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 175 c j 10 100 1000 10000 1 10 100 operation in this area limited by r ds ( on ) single pulse t t = 175 c = 25 c j c v , drain-to-source volta g e (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms
irL1404S/irl1404l www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature v ds 90% 10% v gs t d(on) t r t d(off) t f v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10v + - v dd 25 50 75 100 125 150 175 0 40 80 120 160 t , case temperature ( c) i , drain current (a) c d limited by package 0.001 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. dut y factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)
irL1404S/irl1404l 6 www.irf.com q g q gs q gd v g charge d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - 10 v fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v 25 50 75 100 125 150 175 0 200 400 600 800 1000 1200 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom 39a 67a 95a
irL1404S/irl1404l www.irf.com 7 peak diode recovery dv/dt test circuit p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - r g v dd ? dv/dt controlled by r g ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t * circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer * reverse polarity of d.u.t for p-channel v gs [ ] [ ] *** v gs = 5.0v for logic level and 3v drive devices [ ] *** fig 14. for n-channel hexfet ? power mosfets
irL1404S/irl1404l 8 www.irf.com d 2 pak package outline d 2 pak part marking information 10.16 (.400) re f. 6.47 (.255) 6.18 (.243) 2.61 (.103) 2.32 (.091) 8.89 (.350) r e f. - b - 1.32 (.052) 1.22 (.048) 2.79 (.110) 2.29 (.090) 1.39 (.055) 1.14 (.045) 5.28 (.208) 4.78 (.188) 4.69 (.185) 4.20 (.165) 10.54 (.415) 10.29 (.405) - a - 2 1 3 15.49 (.610) 14.73 (.580) 3x 0.93 (.037) 0.69 (.027) 5.08 (.200) 3x 1.40 (.055) 1.14 (.045) 1.78 (.070) 1.27 (.050) 1.40 (.055) m ax. notes: 1 dimensions after solder dip. 2 dimensioning & tolerancing per ansi y14.5m, 1982. 3 controlling dimension : inch. 4 heatsink & lead dimensions do not include burrs. 0.55 (.022) 0.46 (.018) 0.25 (.010) m b a m minimum recommended footprint 11.43 (.450) 8.89 (.350) 17.78 (.700) 3.81 (.150) 2.08 (.082) 2x lead assignments 1 - ga te 2 - d r ain 3 - s ou rc e 2.54 (.100) 2x dimensions are shown in millimeters (inches) lot code 8024 as s embled on ww 02, 2000 in the assembly line "l" as s e mb l y lot code int ernational rect ifier logo part number dat e code ye ar 0 = 2000 we e k 02 line l f530s this is an irf530s with
irL1404S/irl1404l www.irf.com 9 to-262 part marking information to-262 package outline dimensions are shown in millimeters (inches) example: this is an irl3103l lot code 1789 assembly part number dat e code we e k 1 9 line c lot code ye ar 7 = 1997 assembled on ww 19, 1997 in the assembly line "c" logo rect ifier int ernat ional
irL1404S/irl1404l 10 www.irf.com dimensions are shown in millimeters (inches) d 2 pak tape & reel information 3 4 4 trr feed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl feed direction 10.90 (.429) 10.70 (.421) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 4.72 (.136) 4.52 (.178) 24.30 (.957) 23.90 (.941) 0.368 (.0145) 0.342 (.0135) 1.60 (.063) 1.50 (.059) 13.50 (.532) 12.80 (.504) 330.00 (14.173) m a x. 27.40 (1.079) 23.90 (.941) 60.00 (2.362) m in. 30.40 (1.197) m ax. 26.40 (1.039) 24.40 (.961) notes : 1. comform s to eia-418. 2. controlling dimension: millimeter. 3. dimension measured @ hub. 4. includes flange distortion @ outer edge. repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) i sd 95a, di/dt 160a/s, v dd v (br)dss , t j 175 c notes: starting t j = 25 c, l = 0.35mh r g = 25 ? , i as = 95a. (see figure 12) pulse width 300s; duty cycle 2%. c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss. calculated continuous current based on maximum allowable junction temperature; for recommended current-handing of the package refer to design tip # 93-4. this is applied to d 2 pak , when mounted on 1" square pcb (fr-4 or g-10 material) . for recommended footprint and soldering techniques refer to application note #an-994. data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on ir ? s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 02/02
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